This invention relates in general to electronic devices and, more particularly, to improved means and methods for providing small high performance devices with sidewall contacts, suitable for use in large scale integrated circuits.
There is an ongoing desire in the semiconductor art to produce transistors having smaller and smaller dimensions. This is because, in many applications faster performance, lower power dissipation and/or more complex circuits can be obtained with smaller devices. This desired has lead to the development of bipolar "pillar" devices. These devices require buried layer conductors which act as sidewall contacts to base and/or collector. Pillar transistors and methods therefor are described, for example, in U.S. Pat. Nos. 4,663,831 and 4,696,097 which are incorporated herein by reference.
High speed operation of semiconductor devices is limited by the resistance of the conducting paths and extrinsic capacitance in the devices. "Pillar" devices such as pedestal-type bipolar transistors have been proposed to improve these limitations. The proposed pedestal bipolar transistors use either doped polycrystalline silicon or a refractory metal for the sidewall contacts.
To fabricate a pedestal transistor a well or groove is formed. This well is defined by sidewalls which are made of multilayers of materials. Horizontal layers(s) of polycrystalline silicon or refractory metal act as sidewall contacts. The well is then filled by the selective epitaxial silicon. During the epitaxial growth of silicon, nucleation of polycrystalline silicon at the sidewall of the well can inevitably occur. The silicon nuclei grows as epitaxial silicon and results in polysilicon bumps surrounding the edges of the device. This creates non-planarity in the surface of the wafer which is undesirable for integrated circuit applications. The polycrystalline silicon contact also has a high resistivity which slows the operating speed of a semiconductor device. The polysilicon may also extend into critical device regions within the pillar and thereby further degrade device performance.
While metal contacts have very low resistivity the silicon epitaxial layer can be contaminated by the metal when a refractory metal is used as a conducting path. The use of metal contacts can also degrade the device performance due to the lowering of minority carrier lifetime and increasing leakage currents.